SPI Controller

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Overview

The PE-AHB IP includes the arbiter, decoder and logic controller as described in the AMBA 2.0 Specification.

The IP was also carefully tested by our robust regression test system, verified both the functionality of the controller and the compatibility of the IP with AHB interface. The PE-AHB was not only tested on VCS tool but also on FPGA devices.

icdrec_pe_ahb_ds_1

Features

  • Support burst transfer with all types: SINGLE, INCR, WRAP4, INCR4, WRAP8,INCR8, WRAP16, INCR16
  • Support all burst sizes: byte, half-word, word …
  • Two-state pipeline transfer
  • Configurable Number of Master:
    • AHB Lite (1 Master)
    • AHB Non-Lite (2 to 15 Masters)
  • Configurable Number of Master: 1 to 15 Slaves
  • Support default Master: configurable Default Master ID
  • Configurable Address bus 32/64 bit
  • Configurable data bus width 8/16/32/64/128/256
  • Configurable Endianness: Little Endian or Big Endian
  • Split capable (configurable)
  • Support Early Burst termination for INCR burst (configurable)
  • Priority of Masters (configurable)
    • Fixed priority or
    • Round Robin
    • Programmable
      • Fixed priority based on master index when 2 or more masters have same priority
      • Round robin when 2 or more masters have same priority
  • Support AHB Lite/ Non AHB Lite
  • Decoder:
    • Configurable remap feature (select Boot/ Normal Mode)
  • Configurable whether HPROT signal is available of not

icdrec_pe_ahb_ds_2

Datasheet