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The DCT-FI IP was a low-cost, high performance 2D Forward/Inverse Discrete Cosine Transform. Able to operate over 8×8 blocks of samples/DCT coefficients, the DCT-FI is compliant with most of image/video compression standard. The switching of the direction is easily handled by turning on/off an input signal. One instantiation can be reused for both compress and decompress circuits, thus saving cost for developing products. The DCT-FI was also optimized to provide high clock speed, avoiding bottle neck in the whole system.



Key Features

  • High clock speed, greater than 250 MHz in FPGA technologies
  • Low gate count
  • Runtime reconfigurable direction
  • Streaming interface with packet handle signals.
  • Compliant with JPEG, MPEG standard
  • Support 8-8 and 2-4-8 DCT/IDCT algorithm
  • Registered both input and outputs
  • Synchronous design with positive edge triggered



Logic Memory bit Fmax(MHz) DSP
EP1C6F256C6 2750 2858 133.99
EP1S10F484C5 2264 2858 156.20 14
EP2C5F256C6 2593 2858 168.21 14
EP2S15F484C3 2503 2858 256.48 14


  • RTL Code
  • Verification (Source code)
  • Technical document