PCI Device 2.3

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Overview

The PCI Controller core handles the data transfer between host CPU and the PCI bus device. It performs two flow of transfer:

  • PCI target interface receives data from PCI local bus, encrypt in encrypted block (or not), respond read data to AHB bus request
  • AHB slave interface receives data from AMBA AHB bus, decrypt in decrypted block (or not), respond read data to PCI local bus request.

PCIdiagram

Key features

  • PCI specification 2.3 compliant
    • Zero wait state burst mode
    • 33/66 MHz performance
    • 32/64-bit data path
    • Dual address cycle
    • Memory Read, Memory Write commands
    • Configuration Read and Write commands
    • Fast Back-to-Back Transactions
    • Type 0 Configuration space
  • Interrupt and Status acknowledgment support
  • Parity generation and parity error detection
  • AMBA 2.0 AHB slave interface
  • Synchronous AMBA and PCI clocks
  • Accessible  PCI configuration registers (from both PCI and AHB bus)
  • Enable configuration of SSRAM capacity and FIFO depth
  • Accessible SSRAM from both PCI and AHB bus with the separate memory spaces
  • Optional output encryption and input decryption with AES-128bit

Performance

Logic Memory Fmax DSP
EP3C40F780C6 23,202 (LEs) 2 block of M9K 113Mhz 0
EP3SE50F780C2 9,775 (ALUTs) 2 block of M9K 200 Mhz 0

Delivery

  • RTL Code
  • Verification (Source code)
  • Document

Datasheet