The PE-DMA is a DMA Controller which adopts AHB bus. The IP was carefully tested by our robust regression test system, verified both the functionality of the controller and the compatibility of the IP with AHB interface. The PE-DMA was not only tested on VCS tool but also on FPGA devices.
- Compatible to AMBA AHB 2.0 bus
- Support up to 8 channels with the data width of 32, 64, 128 and 256 bits.
- Each channel can be programmed independently and concurrently
- Support the difference of data width between data from source to DMA and data from DMA to destination for increasing performance of DMA controller.
- Configurable burst transfer size and data buffer size for delivering highest performance
- Support all transfer type: memory to memory, memory to peripheral, peripheral to memory and peripheral to peripheral with the programmable source and destination addresses
- Configurable handshaking protocol between each channel of DMA and peripheral
- Support fixed priority and programmable priority of channels of DMA
|Logic||Memory bit||Fmax||DSP block|
|EP2C35F672C6||7873 (LE)||2560||64 MHz||0|
|EP3C40F780C6||7861 (LE)||2560||71 MHz||0|
- RTL Code
- Verification (Source code)