APB Smart Card Reader

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Overview

The SCR IP implements an interface and controller for communicating between smart card device and the CPU through host system bus.

The core is compatible with the AMBA APB 2.0 bus. It operates as a controller for writing data to and reading data from the smart card and the system bus. It supports the ISO/IEC 7816-3 and EMV200 4.0 specification with full feature.

APB_SCR_diagram

Key features

  • AMBA APB protocol, version 2.0
  • Supports the ISO/IEC 7816-3 and EMV2000 4.
    • Card activation and deactivation
    • Cold/warm reset
    • Answer to Reset (ATR) response reception
  • Data transfers to and  from the card
  • Adjustable clock rate and bit (baud) rate
  • Configurable timing functions:
    • Guard time
    • Timeout timers
    • Buffer timeout
  • Handles commonly used communication protocols:
    • T=0 for asynchronous half-duplex character transmission
    • T=1 for asynchronous half-duplex block transmission
  • Configurable Transmit and Receive FIFO with programmable trigger
  • Automatic convention detection
  • Extensive interrupt support system
    • Configurable automatic byte repetition
    • Prioritized interrupt identification
  • Silent byte generation and detection
  • DMA interface

Performance

Logic Memory Fmax DSP
EP2C35F484C6 1,347 (LEs) 0 141Mhz 0
EP3C10F256C6 1,345 (LEs) 0 164Mhz 0
EP3SE50F780C2 933 (ALUTs) 0 306 Mhz 0

Delivery

  • RTL Code
  • Verification (Source code)
  • Document

Datasheet