32-bit I2C Controller

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Overview

The I2C Controller provides a serial interface according to the Philips I2C specification to communicate with low-speed peripherals. The core can be also integrated into the SoC system through AMBA APB bus. The I2C-APB Controller supports all transfer modes such as high speed mode with maximum 3.4 Mbps of throughput, fast mode with 400kbps of throughput and standard mode with 100kbps of throughput. The controller also supports DMA handshaking interface to communicate with the DMA controller.

I2C32diagram

Key Features

  • Compatible with Philips I2C standard version 2.1.
  • Programmable as I2C master mode.
  • Programmable as I2C slave mode.
  • Multi-master operation.
  • Programmable clock frequency.
  • Clock Stretching and Wait state generation.
  • Programmable ACK bit.
  • Arbitration lost/Bus Error interrupt.
  • Start/Stop/Repeated start generation.
  • Start/Stop detection.
  • Bus busy detection.
  • Support 7 and 10bit of address for both master and slave modes.
  • Support three transferred speeds mode: 100kbps transfer rate in the standard mode, 400kbps in the fast mode and 3.4Mbps in the high speed mode.
  • Designed with AMBA APB (ver. 2.0) interface with the data width of 8/16/32 bit for integrating into the SoC.
  • Internal n x m FIFOs to achieve highest performance of data transfer between I2C and APB, with n= 1÷256, m = 8, 16 or 32.
  • Polling or Interrupted handshake.

Performance

Logic Memory Fmax DSP
EP2C20F484C7 627 2048 133.7 MHz 0
EP2S15F484C3 508 2048 248.88 MHz 0
EP2SGX30CF780C3 511 2048 264 MHz 0

 

Delivery

  • RTL Code
  • Verification (Source code)
  • Document

Datasheet