32-bit UART Controller

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The PE-UART-APB core is a serial communication controller with a serial data that is intended primarily for embedded systems and designing ASIC. The PE-UART-APB core can be used to interface directly to industry standard UARTs.

The IP was carefully tested by our robust regression test system, verified both the functionality of the controller and the compatibility of the IP with AMBA APB interface. The PE-UART-APB was also tested on FPGA devices.


Key Features

  • AMBA APB protocol, version 2.0
  • Configurable parameters for the following:
    • APB data bus widths of 8, 16 and 32
    • DMA interface signal polarity
    • Transmit and receive FIFO depths of none, 16, 32, 64,…,2048
    • Internal or external FIFO (RAM) selection
    • Shadow registers to reduce software overhead and also include a software programmable reset
    • Auto Flow Control mode as specified in the 16750 standard
    • Loopback mode that enables greater testing of Modem Control and Auto Flow Control
    • Transmitter Holding Register Empty (THRE) interrupt mode
    • Busy functionality
  • Functionality based on the 16550 industry standard, as follows:
    • 5, 6, 7 or 8 data bits
    • 1, 1.5 or 2 stop bits
    • Odd, even, space, mark, or no parity
    • Line break generation and detection
    • DMA signaling with two programmable modes
    • Prioritized interrupt identification
  • Programmable FIFO enable/disable
  • Programmable baud rate generator
  • Parity, framing and overflow error detection
  • Line break generation and detection
  • Modem and status lines are independently controlled
  • Local loopback mode
  • Full prioritized interrupt system


Logic Memory Fmax DSP
EP2C35F484C6 1,399 (LEs) 0 153Mhz 0
EP3C10F256C6 1,416 (LEs) 0 181Mhz 0
EP3SE50F780C2 926 (ALUTs) 0 368 Mhz 0


  • Mã nguồn RTL (Verilog HDL)
  • Mã nguồn môi trường kiểm tra (Verilog HDL)
  • Tài liệu kỹ thuật