The SDR SDRAM Controller (SDRC) is designed for use in applications requiring high memory throughput, high clock rates and full programmability.
SDRC accepts the commands from the AMBA 2.0 bus and translates them to the command sequences required by SDR SDRAM devices. Also, SDRC performs complete initialization, auto refresh, and self-refresh functions.
SDRC uses bank management techniques to monitor the status of each SDRAM bank to reduce access time. Up to eight banks can be managed at one time.
SDRC is provided with pre-config timing parameters for all timing parameters (tCL, tRC, tRCD, tRP, tMRD, tRRD, tRFC, tRAS, tWR) and support many kind of AHB burst.
- Compliant to AMBA AHB bus
- Pre-config timing parameters, each controller is dedicated for a specific SDRAM type
- Support multi chip-select signals, can control multi SDRAM at the same time
- Support all kind of AHB burst except WRAP16: SINGLE, INCR, WRAP4, INCR4, WRAP8, INCR8, and INCR16
- Accept Load Mode Register (LMR) command to reprogram the SDRAM in operating time
- Support saving power features by using Self Refresh command
- Support pipelined SDRAM command to achieve high performance
|Cyclone II||146 MHz||716 LEs|
- RTL Code
- Verification (Source Code)