DDR_SDR_C operates at a high performance interface to DDR SDRAM memory devices. The local bus interface transfers read and write commands to the controller. Then DDR_SDR_C receives these commands and translates them the command sequences required by DDR SDRAM devices. DDR_SDR_C also operates all initialization, auto-refresh, and power-down, and self-refresh function for the memory devices.
DDR_SDR_C also uses bank management techniques to track the status of four DDR SDRAM banks. Banks are only opened or closed when it’s necessary to minimize accessing delays.
- Interfaces to industry standard DDR SDRAM
- Programmable burst lengths of 2, 4 or 8
- Programmable CAS Latency of 2, 2.5 or 3 Cycles
- Runtime configurable timing parameters (tRAS, tRC, tRFC, tRP, tMRD, tREFC, tWR, CAS Latency)
- Runtime configurable memory settings (row bits,column Bits)
- Bank Management Tracker Status of Each Bank of DDR SRAM (up to 4 Banks Tracked)
- Automatic generation of initialization and refresh sequences
- Supports auto-precharge commands for optimum random access performance
- Supports self-refresh and power down modes
- Support up to 8 chips, each chip is up to 1GBit of memory
- Supports many standard DDR SDRAM chips and DIMMs
|Stratix II||200 MH||570 ALUTs|
- RTL Code
- Verification (Source Code)