As its predecessor, SigmaK3, the microprocessor VN8_01 is targeted as a low-cost, high performance low power consumption 8-bit CPU employing a modified RISC architecture with separate instruction and data buses. This allows a simultaneous access to program and data memories. The 5-stage pipeline allows VN8_01 to perform 5 instructions at the same time, resulting in a net processing speed 5 times faster than a normal pipeline-less architecture. All instructions are executed in one system clock cycle, except branch instructions in 2 cycles.
Furthermore, a dedicated compiler is developed specially for VN8_01 in order to exploit VN8_01 pipeline architecture to optimize instruction arrangement. This also improves the microprocessor‘s performance.
- CPU’s features
- Harvard RISC 5-stage pipeline architecture
- 37 instructions
- 14-bit instruction width
- Extensible instruction memory up to 64Kx14-bit
- Power saving SLEEP mode
- Synchronous design
- Interrupt controller: 8 interrupted sources
- Four 8-bit bidirectional I/O ports
- Timer0, Timer1, Timer2
- Compare Capture PWM – Pulse-Width Modulation
- Watchdog Timer (8-bit)
- Process: TSMC 0.25um, 5 metal layers
- Core voltage: 2.5V
- PAD voltage: 3.3V
- Core size: 460um x 46um
- Chip size: 20 x 14 x 2.2 mm3.
- Number of pins: 100
- Maximum system clock speed: 100 MHz
- Power consumption: 133 mW