The VN1632 Core is 32-bit microprocessor core developed by ICDREC based on the RISC (Reduced Instruction Set Computer) architecture. The main characteristics are the architecture of Harvard 32-bit RISC but with a five-stage pipeline, in which five successive instructions are loaded simultaneously in five different pipeline stages. As a result, five instructions are executed at the same time. This effectively improves the performance of the microprocessor. It has on-chip cache memory, in which instruction cache and data cache are separate.
The 32-bit microprocessor VN1632 was designed and developed based on the experiences accumulated by the success of other 8-bit microcontrollers. The challenge of this new task was not only the complexity, the larger scale of the 32-bit microprocessor, but to ensure the design originality, many new and hard issues have been studied and implemented: cache memory, prefetch buffer, write buffer, store buffer, bus interface, co-processor, etc
The design has been synthesized, simulated and fabricated using 0.13um IBM process. The result shows that this architecture works correctly with desired performance.
- CPU’s features
- Harvard RISC 5-stage pipeline architecture
- Separate instruction cache and data cache
- Built-in cache memory
- 65 instructions
- 32-bit instruction width
- Multiply in only 2 clock cycles
- Debug support with breakpoint
- Synchronous design
- Bus and Peripherals
- Advance High Performance Bus (AHB)
- Advance Peripheral Bus (APB)
- Memory controller: SDR-SDRAM, Mobile SDR-SDRAM, DDR-SDRAM, or Mobile DDR-SDRAM (LPDDR), SRAMs and FLASHes
- General Purpose I/O (GPIO)
- I2C, I2S
- TIMER 1 and TIMER 2
- UART1, UART2
- Process: IBM 0.13um, 8 metal layers
- Core voltage: 1.2V
- PAD voltage: 2.5V
- Core size: 3560 x 3559 um2.
- Chip size: 24 x 24 x 1.4 mm3, TQFP.
- Number of pins: 176
- Maximum system clock speed: 20 MHz
- Power consumption: 30.6 mW