AMBA AHB Controller

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The PE-AHB IP includes the arbiter, decoder and logic controller as described in the AMBA 2.0 Specification. The IP is highly configurable providing design engineer the flexibility to use it in their desired system.


Key Features

  • All types burst transfer support: SINGLE, INCR, WRAP4, INCR4, WRAP8, INCR8, WRAP16, INCR16
  • All burst sizes support: byte, half-word, word …
  • Two-stage pipeline transfer
  • Configurable number of master:
    • AHB Lite (1 master)
    • AHB Non-Lite (2 to 15 masters)
  • Configurable number of slave: 1 to 15 slaves
  • Configurable default master  ID
  • Configurable address bus width:  32/64 bits
  • Configurable data bus width:  8/16/32/64/128/256
  • Configurable endiannes: little endian or big endian
  • Split capability
  • Early Burst termination for INCR burst
  • Configurable priority of masters:
    • Fixed priority: a master with lower index has higher priority
    • Round robin
    • Programmable priority: user can change priority of master
  • Configurable remap feature (select Boot/ Normal Mode) of decoder
  • Configurable HPROT signal availability.


Logic Memory Fmax DSP
EP2C35F672C6 361 0 159 MHz 0
EP3C40F780C6 367 0 172 MHz 0
EP3SE50F780C2 273(ALUTS) 0 319 MHz 0


  • RTL Code
  • Verification (Source code)
  • Documentation