ARM, Mentor define test flow for ARM CPUs

with No Comments

The reference flow includes documentations, seamless interfaces and scripts that accelerate the development of a test solution for ARM IP based on the Tessent test tools from Mentor, the companies said. The flow is optimized for high test quality, lower test cost and shortened design-for-test development schedules, according to the companies.

ARM (Cambridge, UK) and Mentor (Wilsonville, Ore.) have collaborated to enable Tessent support for the ARM MBIST core interface, which provides one or more interfaces for each embedded core, enabling full testing of every memory within each core with minimum impact on core power, performance or area, the companies said.

The ARM-Mentor test flow supports comprehensive testing of ARM cores and logic, and embedded memories used in customer SoCs, according to the companies. The solution employs the Mentor scan-based design-for-test and automatic test pattern generation tools with embedded compression, as well as memory BIST (built-in self test) with self-repair technologies, the companies said. The test flow defines all steps necessary for incorporating and verifying all test compression and memory BIST IP, as well as generating all necessary test patterns, they said.

“Our joint effort with ARM is extremely beneficial for our mutual customers because it enhances the time-to-market advantages of using ARM IP by helping them achieve their testing objectives in the least amount of time,” said Steve Pateras, product marketing director for Silicon Test Products at Mentor, in a statement.

Also Monday, Mentor announced new capabilities for the Tessent TestKompress and the Tessent FastScan tools that enable higher defect coverage and lower defect-per-million levels for quality-critical applications like military, medical, automotive, and many others. User defined fault models and a new cell-aware ATPG flow together allow customers to target subtle shorts and open defects internal to standard cells that are not adequately detected with the standard stuck-at or transition fault models, Mentor said.


EETimes, 9/19/2011

Archived on Wed, 21/09/2011 – 08:54


SAN FRANCISCO—ARM Holdings plc and Mentor Graphics Corp. said Monday (Sept. 19) they have jointly developed a reference flow for manufacturing test of ARM processor-based designs.