Integrated Circuit Design Research and Education Center
Integrated Circuit Design Research & Education Center (ICDREC) established by Decision No. 42/2005/QĐ/KCNPM on 08 August 2005 of the Director of Viet Nam National University HCMC. ICDREC locates in Viet Nam National University – Information Technology Park (VNU-ITP) at Linh Trung ward, Thu Duc district, HoChiMinh City.
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The PE-AHB IP includes the arbiter, decoder and logic controller as described in the AMBA 2.0 Specification. The IP is highly configurable providing design engineer the flexibility to use it in their desired system.The DCT-FI IP was a low-cost, high performance 2D Forward/Inverse Discrete Cosine Transform. Able to operate over 8×8 blocks of samples/DCT coefficients, the DCT-FI is compliant with most of image/video compression standard. The switching of the direction is easily handled by turning on/off an input signal. One instantiation can be reused for both compress and decompress circuits, thus saving cost for developing products. The DCT-FI was also optimized to provide high clock speed, avoiding bottle neck in the whole system.The MP-VN1632LP is a high-performance and low-power 32-bit microprocessor. The applications range from low-power handsets to high-performance embedded devices. The MP-VN1632LP is based on a high-performance technology - the superscalar. It is a multi-issue, 6-stage Out-of-Order (OoO) architecture. The MP-VN1632LP can operate at high performance 450 DMIPS in 130nm technology at 300MHz (worst case slow corner conditions with production margins). The MP-VN1632LP is fully-synthesizable IP that achieves high frequencies using commercially-available, non-custom, standard cells and memories. The MP-VN1632LP enables flexibility in configuration for specific features, and the ability to migrate your design across foundries, process nodes, and geometries.The SCR IP implements an interface and controller for communicating between smart card device and the CPU through host system bus. The core is compatible with the AMBA APB 2.0 bus. It operates as a controller for writing data to and reading data from the smart card and the system bus. It supports the ISO/IEC 7816-3 and EMV200 4.0 specification with full feature.The SCR IP implements an interface and controller for communicating between smart card device and the CPU through host system bus. The core is compatible with the Avalon Memory Map bus. It operates as a controller for writing data to and reading data from the smart card and the system bus. It supports the ISO/IEC 7816-3 and EMV200 4.0 specification with full feature.
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Address: Floor 7, 6 Quarter, Vietnam National University Ho Chi Minh City Building, Linh Trung Ward, Thu Duc District, Ho Chi Minh City.
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