Specification

     -    Harvard RISC Architecture
     -    2-Stage Pipelined Architecture
     -    33 instructions with 12 bit wide instruction word
     -    Up to 256 bytes of internal data memory
     -    Up to 4K x 12 bits of program
     -    Timer and Watchdog Timer
     -    Power saving SLEEP mode

Technical Characteristics   

    -    Process: TSMC 0.25um, 5 metal layers
    -    Core voltage: 2.5V
    -    PAD voltage: 3.3V
    -    Core size: 3 x 3 mm2.
    -    Chip size: 14 x 14 x 1.4 mm3, QFP.
    -    Number of pins: 100
    -    Maximum system clock speed: 50 MHz
    -    Power consumption: 51 mW